ADT7463
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47
Table 77. REGISTER 0X75 INTERRUPT MASK REGISTER 2 (POWERON DEFAULT = 0X00)
Bit
Name
R/W
Description
0
12V/VC
R/W
A 1 masks SMBALERT
for outoflimit conditions on the 12 V channel.
1
OVT
Readonly
A 1 masks SMBALERT
for overtemperature THERM
conditions.
2
FAN1
R/W
A 1 masks SMBALERT
for a Fan 1 fault.
3
FAN2
R/W
A 1 masks SMBALERT
for a Fan 2 fault.
4
FAN3
R/W
A 1 masks SMBALERT
for a Fan 3 fault.
5
F4P
R/W
A 1 masks SMBALERT
for a Fan 4 fault. If the TACH4 pin is being used as the THERM
input,
this bit masks SMBALERT
for a THERM
timer event.
6
D1
R/W
A 1 masks SMBALERT
for a diode open or short on Remote 1 channel.
7
D2
R/W
A 1 masks SMBALERT
for a diode open or short on Remote 2 channel.
Table 78. REGISTER 0X76 EXTENDED RESOLUTION REGISTER 1
Bit
Name
R/W
Description
<1:0>
12V
Readonly
2.5 V LSBs. Holds the 2 LSBs of the 10bit 2.5 V measurement.
<3:2>
V
CCP
Readonly
V
CCP
LSBs. Holds the 2 LSBs of the 10bit V
CCP
measurement.
<5:4>
V
CC
Readonly
V
CC
LSBs. Holds the 2 LSBs of the 10bit V
CC
measurement.
<7:6>
5V
Readonly
5 V LSBs. Holds the 2 LSBs of the 10bit 5 V measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 79. REGISTER 0X77 EXTENDED RESOLUTION REGISTER 2 (Note 1)
Bit
Name
R/W
Description
<1:0>
12V
Readonly
12 V LSBs. Holds the 2 LSBs of the 10bit 12 V measurement.
<3:2>
TDM1
Readonly
Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10bit Remote 1 temperature
measurement.
<5:4>
LTMP
Readonly
Local Temperature LSBs. Holds the 2 LSBs of the 10bit local temperature measurement.
<7:6>
TDM2
Readonly
Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10bit Remote 2 temperature
measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 80. REGISTER 0X78 CONFIGURATION REGISTER 3 (POWERON DEFAULT = 0X00) (Note 1)
Bit
Name
R/W
Description
<0>
ALERT
R/W
ALERT = 1, Pin 10 (PWM2/ SMBALERT
) is configured as an SMBALERT
interrupt output to
indicate outoflimit error conditions.
<1>
THERM
ENABLE
R/W
THERM
ENABLE = 1 enables THERM
monitoring functionality on the pin determined by
Bit 1 (TH5V) of Configuration Register 4.
When THERM
is asserted, fans can be run at full speed (if the BOOST bit is set), or a timer can
be triggered to time how long THERM
has been asserted for.
<2>
BOOST
R/W
BOOST = 1, assertion of THERM
causes all fans to run at 100% duty cycle for failsafe cooling.
<3>
FAST
R/W
FAST = 1 enables fast TACH measurements on all channels. This increases the TACH
measurement rate from once per second, to once every 250 ms (4?.
<4>
DC1
R/W
DC1 = 1 enables TACH measurements to be continuously made on TACH1.
<5>
DC2
R/W
DC2 = 2 enables TACH measurements to be continuously made on TACH2.
<6>
DC3
R/W
DC3 = 1 enables TACH measurements to be continuously made on TACH3.
<7>
DC4
R/W
DC4 = 1 enables TACH measurements to be continuously made on TACH4.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
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